FIG. 10 is a schematic diagram illustrating the configuration of a conventional system. As illustrated in FIG. 10, the system includes system boards 10a and 10b, IO boards 20a and 20b, a crossbar 30, and a system management device 40. The system boards 10a and 10b each include central processing units (CPUs), a memory, and a system control circuit that controls, for example, data communication with another large scale integration (LSI). The system boards 10a and 10b are connected to the crossbar 30 and perform data communication with, for example, the IO boards 20a and 20b, respectively.
The IO boards 20a and 20b each include an IO control circuit that controls, for example, data communication with another LSI. The IO boards 20a and 20b are connected to the crossbar 30 and perform data communication with, for example, the system boards 10a and 10b, respectively. When the system boards 10a and 10b and the IO boards 20a and 20b perform data communication, a device that transmits data and a device that receives data adjust the phase of a clock (see, Patent Document 1). In the following description, the device that transmits data is referred to as a transmission LSI and the device that receives data is referred to as a receiving LSI.
The system management device 40 is connected to the transmission LSI and the receiving LSI (e.g., the system control circuits and the IO control circuits), controls the operation timing of the phase adjustment of the clock performed in each control circuit, collects a log of errors occurring in each LSI, and the like.
The transmission LSI and the receiving LSI respectively transmit data to and receive data from each other at high speed using signals with various bit widths. FIG. 11 is a schematic diagram illustrating the connection relation between the transmission LSI and the receiving LSI. As illustrated in FIG. 11, a transmission LSI 50 and a receiving LSI 60 are connected by N signal lines (N is a positive integer). Specifically, the transmission LSI 50 and the receiving LSI 60 perform data communication using an N-bit transmission path. When performing the phase adjustment as a preparation for the data transfer, the receiving LSI 60 performs the phase adjustment by receiving both a data pattern and a clock that are transmitted from the transmission LSI 50.
FIG. 12 is a schematic diagram illustrating the configuration of the conventional transmission LSI 50 and the conventional receiving LSI 60. As illustrated in FIG. 12, the transmission LSI 50 includes a degeneracy processing unit 51, a transmission data processing unit 52, a pattern creating unit 53, a phase adjustment control circuit 54, data selection circuits 55-1 to 55-N, a PLL 56, latches (flip-flop circuits) 57-1 to 57-N, a clock output circuit 58, and data output circuits 59-1 to 59-N.
The receiving LSI 60 includes a clock input circuit 61, data input circuits 62-1 to 62-N, latches (flip-flop circuits) 63-1 to 63-N, phase adjustment circuits 64-1 to 64-N, phase adjustment control circuits 65-1 to 65-N, a phase adjustment instruction circuit 66, a degeneracy processing unit 67, and a receiving-data processing unit 68.
In the following description, the configuration of the transmission LSI 50 will be described first and then the configuration of the receiving LSI 60 will be described. The degeneracy processing unit 51 is a processing unit that detects a failure of a signal line connected to the transmission LSI 50 and the receiving LSI 60 and outputs, to the transmission data processing unit 52 as a usage bit selection signal, information on a signal line in which a failure has not occurred.
The transmission data processing unit 52 is a processing unit that obtains a usage bit selection signal and transmits transmission data to a data selection circuit by using a signal line in which a failure has not occurred. If no failure occurs in each of the signal lines 1 to N, the transmission data processing unit 52 transmits transmission data 1 to N to the data selection circuits 55-1 to 55-N, respectively. For example, if a failure occurs in a signal line N-M (M is a positive integer), the transmission data processing unit 52 outputs the corresponding transmission data to a data selection circuit other than the data selection circuit N-M.
The pattern creating unit 53 is a processing unit that creates a training pattern and outputs the created training pattern to the data selection circuits 55-1 to 55-N. The phase adjustment control circuit 54 is a processing unit that outputs a transmission data selection signal to the data selection circuits 55-1 to 55-N when a phase adjustment instruction is received from the system management device 40.
A data selection circuit 55-j (j is a positive integer equal to or greater than one and equal to or less than N; this also applies to j described below) is a circuit that obtains both transmission data and a training pattern and outputs, to a latch 57-j depending on whether a transmission data selection signal is received, the transmission data or the training pattern. Specifically, if the data selection circuit 55-j obtains a transmission data selection signal from the phase adjustment control circuit 54, the data selection circuit 55-j outputs the transmission data to the latch 57-j. In contrast, if the data selection circuit 55-j does not receive a transmission data selection signal, it outputs the training pattern to the latch 57-j. 
The PLL 56 is a device that creates a clock and outputs the created clock to the latches 57-1 to 57-N and the clock output circuit 58. The latch 57-j is a circuit that obtains data (transmission data or a training pattern) in accordance with the rising and the falling of the clock and outputs the obtained data to a data output circuit 59-j. 
The clock output circuit 58 is a circuit that transmits, to the clock input circuit 61 in the receiving LSI 60, the clock obtained from the PLL 56. The data output circuit 59-j is a circuit that transmits, to a data input circuit 62-j in the receiving LSI 60, data (transmission data or a training pattern) obtained from the latch 57-j. 
In the following, the configuration of the receiving LSI 60 will be described. The clock input circuit 61 is a circuit that receives a clock from the clock output circuit 58 in the transmission LSI 50 and outputs the received clock to the phase adjustment circuits 64-1 to 64-N.
The data input circuit 62-j is a circuit that receives data (transmission data or a training pattern) from the data output circuit 59-j in the transmission LSI 50 and outputs the received data to a latch 63-j. 
The latch 63-j is a circuit that obtains the adjusted clock from a phase adjustment circuit 64-j and, in accordance with the rising and the falling of the clock, outputs, to a phase adjustment control circuit 65-j and the receiving-data processing unit 68, the data obtained from the data input circuit 62-j. 
The phase adjustment circuit 64-j is a circuit that adjusts, in accordance with a TAP value (an adjustment value of the phase) obtained from the phase adjustment control circuit 65-j, the phase of the clock obtained from the clock input circuit 61 and outputs the adjusted clock to the latch 63-j. 
FIG. 13 is a schematic diagram illustrating an example configuration of the phase adjustment circuit 64-j. As illustrated in FIG. 13, the phase adjustment circuit 64-j includes buffer circuits 64a, a decoder 64b, switches 64c, and capacitors 64d. 
By turning on and off the switches 64c in accordance with the TAP value, the decoder 64b changes a load capacity of the path (delay line) passing through the buffer circuits 64a. Accordingly, the amount of delay in the delay line is controlled, and thus the phase of the clock signal varies. As the number of turned-on switches increases, the load capacity increases and thus the amount of delay also increases.
The phase adjustment control circuit 65-j is a circuit that obtains a training pattern from the latch 63-j when obtaining an adjustment instruction from the phase adjustment instruction circuit 66 and determines a TAP value in accordance with the obtained training pattern. FIG. 14 is a schematic diagram illustrating an example configuration of a phase adjustment control circuit. As illustrated in FIG. 14, the phase adjustment control circuit 65-j includes an expected value creating unit 65a, a data comparison unit 65b, and a control unit 65c. The expected value creating unit 65a is a processing unit that creates a training pattern and outputs the created training pattern to the data comparison unit 65b at a predetermined clock timing.
The data comparison unit 65b is a processing unit that sequentially compares the training pattern obtained from the latch 63-j and the training pattern obtained from the expected value creating unit 65a and sequentially outputs the comparison result to the control unit 65c. In the following description, the training pattern obtained from the latch 63-j is referred to as a first training pattern and the training pattern obtained from the expected value creating unit 65a is referred to as a second training pattern.
The control unit 65c is a processing unit that obtains the comparison result from the data comparison unit 65b, determines the TAP value in accordance with the comparison result, and outputs the determined TAP value to the phase adjustment circuit 64-j. For example, if the first training pattern and the second training pattern do not match, the control unit 65c outputs, to the phase adjustment circuit 64-j, a TAP value obtained by adding a predetermined value to the TAP that is previously output. If the first training pattern and the second training pattern do match, the control unit 65c outputs, to the phase adjustment circuit 64-j, a TAP value obtained by subtracting a predetermined value from the previously obtained TAP value.
Refer back to FIG. 12. The phase adjustment instruction circuit 66 is a circuit that outputs the adjustment instruction to the phase adjustment control circuits 65-1 to 65-N when a phase adjustment instruction is received from the system management device 40.
The degeneracy processing unit 67 is a processing unit that detects a failure of the signal line that connects the transmission LSI 50 and the receiving LSI 60 and outputs, to the receiving-data processing unit 68 as a usage bit selection signal, information on a signal line in which a failure has not occurred. The receiving-data processing unit 68 is a processing unit that obtains the usage bit selection signal, receives data transmitted from the signal line in which a failure has not occurred, and performs various processes.
In the following, the phase adjustment of the receiving LSI 60 will be described. FIG. 15 is a schematic diagram illustrating the conventional phase adjustment. In FIG. 15, an FF input data 1-A is a training pattern that is output from the data input circuit 62-j to the latch 63-j. A clock 1-B is a clock that is output, before the phase adjustment, from the phase adjustment circuit 64-j to the latch 63-j. 
FF output data 1-C is a training pattern that is output, before the phase adjustment, from the latch 63-j to the phase adjustment control circuit 65-1. Expected receiving data 1-D is a training pattern that is output from the expected value creating unit 65a to the data comparison unit 65b. A comparison result 1-E is data that is output, before the phase adjustment, from the data comparison unit 65b to the control unit 65c. 
A clock 2-B is a clock that is output, after the phase adjustment, from the phase adjustment circuit 64-j to the latch 63-j. FF output data 2-C is a training pattern that is output, after the phase adjustment, from the latch 63-j to the phase adjustment control circuit 65-1. A comparison result 2-E is data that is output, after the phase adjustment, from the data comparison unit 65b to the control unit 65c. 
As illustrated in FIG. 15, before the phase adjustment, the timing of the rising and the falling of the clock 1-B is shifted from the center of the data waveform of the FF input data 1-A. Accordingly, the FF output data 1-C and the expected receiving data 1-D are shifted, and thus no comparison result can be used.
However, because the receiving LSI 60 adjusts the phase of the clock, the timing of the rising and the falling of the clock 2-B is adjusted to the center of the data waveform of the FF input data 1-A. Accordingly, each timing of the FF output data 2-C and expected receiving data 2-D matches, and thus all of the comparison results can be used. In this way, the preparation of the data transfer is completed; therefore, the receiving LSI 60 can normally receive data from the transmission LSI 50.
Even when the receiving LSI 60 performs the phase adjustment of the clock as described above, because the phase of the clock varies in accordance with an environmental change due to a temperature change or a voltage change, the phase of the clock is not optimum. FIG. 16 is a schematic diagram illustrating a phase change in a clock where the phase change is generated due to an environmental change.
As illustrated in the upper portion of FIG. 16, immediately after the phase adjustment, the timing of the rising and the falling of the clock is adjusted to the center of the data waveform of the FF input data. However, as illustrated in the middle portion of FIG. 16, after a predetermined time has elapsed, the timing of the rising and the falling of the clock is shifted from the center of the data waveform of the FF input data due to an environmental change.
If the timing of the rising and the falling of the clock is shifted from the center of the data waveform of the FF input data, the receiving LSI 60 does not appropriately receive the data; therefore, it is preferable to periodically adjust the phase of the clock even after the data transfer has been started. Accordingly, even after the data transfer has been started, the conventional transmission LSI 50 and the conventional receiving LSI 60 readjust the phase of the clock for a predetermined period of time.
As illustrated in the lower portion of FIG. 16, by readjusting the phase of the clock, the timing of the rising and the falling of the clock is adjusted to the center of the data waveform of the FF input data. If the transmission LSI 50 and the receiving LSI 60 readjust the phase of the clock, they temporarily suspend the data transfer and readjust the phase.
Patent Document 1: Japanese Laid-open Patent Publication No. 2006-050102
However, with the conventional technology, because the phase of the clock is adjusted by suspending the data transfer for a predetermined period of time, the data transfer is temporarily delayed, and thus the data transfer rate is reduced.
If the data transfer rate is reduced, the performance of the entire system, including the transmission LSI 50 and the receiving LSI 60, is reduced. Accordingly, maintaining the optimum phase of a clock without delaying the data transfer is an important factor.
Accordingly, the present invention has been conceived in light of the circumstances described above, and an object thereof is to provide a data transfer unit, a data transmission device, and a data receiving device that can maintain the optimum phase of a clock without delaying the data transfer and a control method of the same.